1. Field of the Invention
The invention relates to a layout apparatus for a semiconductor integrated circuit (LSI) and a method therefor, and more particularly to a layout apparatus to make layout by collating a circuit represented by clusters with cells stored in a cell library and a method therefor.
2. Description of the Related Art
Improvement of an integration degree of LSIs is outstanding these years, and development costs for preparing a mask pattern are required in a large amount accordingly. Therefore, it is significant to use an automatic mask pattern preparing system.
Conventional automatic LSI producing methods which prepare automatically a mask pattern by entering connection descriptions of a transistor level include the following two methods.
(1) A method of arranging transistors one-dimensionally (single row).
(2) A method of using a layout cell library capable of changing a predefined transistor size.
The method of arranging transistors in a row can form a mask pattern regardless of whatever connection a given connection description has. Specifically, FIG. 7 shows that transistor regions 713 are sequentially arranged on a mask pattern 710 to determine an available region 711. But, when the transistor regions 713 do not have the same size (transistor size), there is a useless region as an unused region 712. Therefore, a signal wiring length becomes long but it is disadvantageous in view of electrical characteristics. Accordingly, this method cannot be used for the LSI which requires predetermined characteristics in a predetermined area.
And, the method which uses a layout cell library is advantageous to reduce an LSI area and to obtain a predetermined performance. But, a perfect mask pattern cannot be formed if a given connection description has a portion which is not defined in the layout cell library. Therefore, to achieve the method using a layout cell library, it is necessary that a given connection description is divided into optimum small blocks, and these small blocks are determined whether they have the same pattern with the cells registered in the layout cell library. This same pattern determining method includes, for example, a method disclosed in "Circuit Comparison by Pattern Matching" given on pp290 to 293 of "ICCAD '91" (IEEE). The method given in this publication compares sequentially the given connection descriptions with predefined connection patterns for each connection hierarchy to recognize the pertinent circuit block.
Generally, it is very significant to reduce the area of a mask pattern in producing an LSI, and it is necessary to suppress an unused region from being formed as much as possible. Therefore, in addition to NAND gates, inverters and other basic gates registered in the layout cell library, it is necessary to register cell patterns which are configured by combining a plurality of them.
But, as shown in FIG. 8, when the connection description of a circuit consisting of an A circuit 801 which comprises a switch (gate) circuit 803A, a half of a switch circuit 803B and a buffer circuit 804 and a B circuit 802 which comprises a half of the switch circuit 803B and an output transistor 805 is compared with the connection pattern, the A circuit 801 and the B circuit 802 cannot be recognized if the switch circuit 803 and the connection pattern are mutually matched in advance. In such a case, a mask pattern using the cell patterns of the circuit 801 and the circuit 802 can be corresponded by two blocks as shown in FIG. 9A, but a mask pattern using the cell patterns of the circuits 803A, 804, 803B and 805 needs four blocks as shown in FIG. 9B. Specifically, the unused region is small when the cell patterns of the A circuit 801 and the B circuit 802 are used. Therefore, the pertinent cell pattern cannot be used, and when the cell patterns of the circuits 803A, 804, 803B and 805 are used, the mask pattern becomes large, and a chip area becomes also large.
As described above, conventional LSI layout technologies cannot apply an appropriate connection pattern depending on a circuit structure and cannot always use the chip area effectively.